The present invention relates to a semiconductor technology, and more particularly, to a programming method of a non-volatile memory device.
Recently, there are growing demands for semiconductor memory devices that can electrically erase and program data without refreshing stored data. Also, the mainstream technology is to increase storage capacity and integration density of semiconductor memory devices. A NAND flash memory device is one of non-volatile semiconductor memory devices that provide high capacity and high integration density without refreshing the stored data. Since a NAND flash memory device retains data even when power is off, it is widely used in electronic devices in which power supply may be abruptly interrupted, for example, portable terminals, laptop computers, and so forth.
A NAND flash memory device includes an array of memory cells comprising floating gate transistors. The array includes unit strings including memory cells, and the memory cells are serially connected between a drain select transistor and a source select transistor. A plurality of word lines are arranged to intersect the strings. The word lines are connected to control gates of the memory cells corresponding to the strings, respectively.
A programming operation of a typical NAND flash memory device will be described below.
First, a voltage of 0 V is applied to a selected bit line connected to a selected memory cell, and a program voltage VPGM is applied to the selected word line connected to the selected memory cell. In this way, electrons of a channel are injected into a floating gate by FN tunneling caused by a high voltage difference between a channel of the memory cell and a control gate. At this point, a pass voltage VPASS for transferring data (0 V) applied to the selected bit line to the selected memory cell is applied to unselected word lines connected to unselected memory cells among a plurality of memory cells disposed between a bit line and a ground terminal.
Although the program voltage VPGM is generally 18 V, it may be applied in a range between 16 V and 19 V by using an Incremental Step Pulse Programming (ISPP) scheme having a waveform diagram of FIG. 1 according to a program cycle in order to improve programming distribution. The pass voltage VPASS is applied with a fixed voltage of approximately 9 V.
A problem may occur when the selected memory cells connected to the corresponding word line are programmed without programming the unselected memory cells connected to the selected bit line. When the program voltage VPGM is applied to the selected word line, the program voltage VPGM is applied to the unselected memory cells arranged along the word line, as well as the selected memory cell. Thus, the unselected memory cells connected to the selected word line, especially the unselected memory cells adjacent to the selected memory cell, may be programmed. Such an unintended programming of the unselected memory cells connected to the selected word line is referred to as a program disturbance.
As one of technologies for preventing the program disturbance, a program inhibition method using a self boosting scheme has been proposed. The program inhibition method using the self boosting scheme is disclosed in U.S. patent application No. 5,677,873, entitled “Method Of Programming Flash EEPROM Integrated Circuit Memory Devices to Prevent Inadvertent Programming of Nondesignated NAND Flash Memory Cells Therein,” and U.S. patent application No. 5,991,202, entitled “Method for Reducing Program Disturb During Self-Boosting In A NAND Flash Memory.”
The program inhibition method using the self boosting scheme will be described below in detail with reference to FIG. 2.
First, a ground path is interrupted by applying a voltage of 0 V to a gate of a source select transistor SST. A voltage of 0 V is applied to a selected bit line, and a power supply voltage VCC of 3.3 V or 5 V is applied to unselected bit lines as a program inhibition voltage. Simultaneously, a source of a drain select transistor DST is charged to VCC-VTH (where VTH is a threshold voltage of the drain select transistor DST) by applying the power supply voltage VCC to a gate of the drain select transistor DST, and the drain select transistor DST is then substantially turned off. A program voltage VPGM is applied to a selected word line and a pass voltage VPASS is applied to unselected word lines, so that a channel voltage of a program-inhibited memory cell is boosted. The boosted channel voltage makes FN tunneling not occur between a floating gate and a channel. Consequently, the program-inhibited memory cell is kept in an initial erased state.
As another technology, a program inhibition method using a local self boosting scheme has been proposed. The program inhibition method using the local self boosting scheme is disclosed in U.S. patent application No. 5,715,194, entitled “Bias Scheme of Program Inhibit for Random Programming in a NAND Flash Memory,” and U.S. patent application No. 6,061,270, entitled “Method for Programming a Non-Volatile Memory Device With Program Disturb Control.”
The program inhibition method using the local self boosting scheme will be described in detail with reference to FIG. 3.
First, a ground path is interrupted by applying a voltage of 0 V to a gate of a source select transistor SST. A voltage of 0 V is applied to a selected bit line, and a power supply voltage VCC of 3.3 V or 5 V is applied to unselected bit lines as a program inhibition voltage. Simultaneously, a source of a drain select transistor DST is charged to VCC-VTH (where VTH is a threshold voltage of the drain select transistor DST) by applying the power supply voltage VCC to a gate of the drain select transistor DST, and the drain select transistor DST is then substantially turned off. A decoupling voltage VDCP of 0 V is applied to unselected word lines (for example, WL13 and WL15) immediately adjacent to a selected word line (for example, WL14), and a pass voltage VPASS is applied to the other unselected word lines. A program voltage VPGM is applied to the selected word line (for example, WL14). Consequently, like the self boosting scheme, the boosted channel voltage makes FN tunneling not occur between a floating gate and a channel of a program-inhibited memory cell. Thus, the program-inhibited memory cell is kept in an initial erased state.
According to the local self boosting scheme, the channel of the program-inhibited memory cell is restricted by memory cells connected to the unselected word lines to which the decoupling voltage VDCP is supplied. Therefore, the boosted channel voltage of the program-inhibited memory cell is further increased compared with the self boosting scheme.
The local self boosting scheme that can obtain higher channel voltage than the self boosting scheme is mainly used to program multi-level cells (MLC) that can store data of 2 bits or more. However, compared with the self boosting scheme, the local self boosting scheme has limitations in that a program speed is reduced.
FIG. 4 is a graph showing comparison of program threshold voltages PGM_VT in the self boosting scheme A and the local self boosting scheme B, that is, the program speed. It can be seen from FIG. 4 that the program threshold voltage in the local self boosting scheme B is reduced by approximately 300 mV to approximately 500 mV compared with the self boosting scheme A.
The cause of the reduction of the program speed in the local self boosting scheme is as follows. Generally, the program threshold voltage (that is, the voltage of the floating gate of the memory cell to be programmed) is affected by a capacitive coupling from the voltages of the floating gates of other memory cells. However, in the case of the local self boosting scheme, a decoupling voltage VDCP of 0 V is applied to word lines of the memory cells disposed on both sides of the memory cell to be programmed, and the program threshold voltage is not affected by the voltages of the floating gates disposed on both sides. For this reason, the program threshold voltage, that is, the program speed, is further reduced in the local self boosting scheme than in the self boosting scheme. The program speed could be increased by increasing the pass voltage VPASS. However, if a high pass voltage VPASS is used, disturbance characteristics of edge memory cells MC0 and MC15 adjacent to the select transistors DST and SST will be degraded.